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TVLSI
2008
150views more  TVLSI 2008»
13 years 8 months ago
Data Memory Subsystem Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance o...
M. Bennaser, Yao Guo, Csaba Andras Moritz
SPAA
1996
ACM
14 years 26 days ago
From AAPC Algorithms to High Performance Permutation Routing and Sorting
Several recent papers have proposed or analyzed optimal algorithms to route all-to-all personalizedcommunication (AAPC) over communication networks such as meshes, hypercubes and ...
Thomas Stricker, Jonathan C. Hardwick
DPD
2006
141views more  DPD 2006»
13 years 8 months ago
Efficient parallel processing of range queries through replicated declustering
A common technique used to minimize I/O in data intensive applications is data declustering over parallel servers. This technique involves distributing data among several disks so...
Hakan Ferhatosmanoglu, Ali Saman Tosun, Guadalupe ...
IPPS
2009
IEEE
14 years 3 months ago
Early experiences on accelerating Dijkstra's algorithm using transactional memory
In this paper we use Dijkstra’s algorithm as a challenging, hard to parallelize paradigm to test the efficacy of several parallelization techniques in a multicore architecture....
Nikos Anastopoulos, Konstantinos Nikas, Georgios I...
ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
14 years 3 months ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...