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ISCA
2006
IEEE
144views Hardware» more  ISCA 2006»
13 years 7 months ago
Conditional Memory Ordering
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by ...
Christoph von Praun, Harold W. Cain, Jong-Deok Cho...
MICRO
2005
IEEE
110views Hardware» more  MICRO 2005»
14 years 1 months ago
Scalable Store-Load Forwarding via Store Queue Index Prediction
Conventional processors use a fully-associative store queue (SQ) to implement store-load forwarding. Associative search latency does not scale well to capacities and bandwidths re...
Tingting Sha, Milo M. K. Martin, Amir Roth
CAV
2009
Springer
136views Hardware» more  CAV 2009»
14 years 8 months ago
Intra-module Inference
Abstract. Contract-based property checkers hold the potential for precise, scalable, and incremental reasoning. However, it is difficult to apply such checkers to large program mod...
Shuvendu K. Lahiri, Shaz Qadeer, Juan P. Galeotti,...
CCGRID
2010
IEEE
13 years 8 months ago
Designing Accelerator-Based Distributed Systems for High Performance
Abstract--Multi-core processors with accelerators are becoming commodity components for high-performance computing at scale. While accelerator-based processors have been studied in...
M. Mustafa Rafique, Ali Raza Butt, Dimitrios S. Ni...
PETRA
2009
ACM
14 years 2 months ago
Towards faster activity search using embedding-based subsequence matching
Event search is the problem of identifying events or activity of interest in a large database storing long sequences of activity. In this paper, our topic is the problem of identi...
Panagiotis Papapetrou, Paul Doliotis, Vassilis Ath...