37 search results - page 6 / 8 » Improving Execution Speed of FPGA using Dynamically Reconfig... |
ASAP
2007
IEEE
14 years 1 months ago
2007
IEEE
We present a memory efficient, practical, systolic, parallel architecture for the complete 0/1 knapsack dynamic programming problem, including backtracking. This problem was inte...
JUCS
2006
13 years 7 months ago
2006
: Several techniques for implementing Prolog in a efficient manner have been devised since the original interpreter, many of them aimed at achieving more speed. There are two main ...
ISCA
1997
IEEE
13 years 11 months ago
1997
IEEE
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...
IJPP
2002
13 years 7 months ago
2002
This paper presents a compilation framework that allows executable code to be shared across different Java Virtual Machine (JVM) instances. All fully compliant JVMs that target se...
DDECS
2008
IEEE
14 years 1 months ago
2008
IEEE
Abstract—In Network-on-Chip (NoC) application design, coreto-node mapping is an important but intractable optimization problem. In the paper, we use simulated annealing to tackle...