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» Improving Java performance using hardware translation
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105
Voted
ICCD
2008
IEEE
159views Hardware» more  ICCD 2008»
15 years 11 months ago
Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor
— Heterogeneous Chip Multiprocessors (HMPs), such as the Cell Broadband Engine, offer a new design optimization opportunity by allowing designers to provide accelerators for appl...
Michael Gschwind
133
Voted
COLING
2008
15 years 3 months ago
Domain Adaptation for Statistical Machine Translation with Domain Dictionary and Monolingual Corpora
tra Statistical machine translation systems are usually trained on large amounts of bilingual text and monolingual text. In this paper, we propose a method to perform domain adapta...
Hua Wu, Haifeng Wang, Chengqing Zong
CSL
2011
Springer
14 years 9 months ago
Syntax-based reordering for statistical machine translation
In this paper we address the problem of translating between languages with word order disparity. The idea of augmenting statistical machine translation (SMT) by using a syntax-bas...
Maxim Khalilov, José A. R. Fonollosa
ISCA
1993
IEEE
137views Hardware» more  ISCA 1993»
15 years 6 months ago
Architectural Support for Translation Table Management in Large Address Space Machines
Virtual memoy page translation tables provide mappings from virtual to physical addresses. When the hardware controlled Tratmlation L.ookaside Buffers (TLBs) do not contain a tran...
Jerome C. Huck, Jim Hays
EMNLP
2010
15 years 12 days ago
Minimum Error Rate Training by Sampling the Translation Lattice
Minimum Error Rate Training is the algorithm for log-linear model parameter training most used in state-of-the-art Statistical Machine Translation systems. In its original formula...
Samidh Chatterjee, Nicola Cancedda