2032 search results - page 348 / 407 » Improving Java performance using hardware translation |
118
Voted
IPPS
2009
IEEE
15 years 9 months ago
2009
IEEE
Various studies have shown that OS jitter can degrade parallel program performance considerably at large processor counts. Most sources of system jitter fall broadly into 5 catego...
105
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ISCA
2002
IEEE
15 years 7 months ago
2002
IEEE
This paper investigates a class of main memory accesses (invalid memory traffic) that can be eliminated altogether. Invalid memory traffic is real data traffic that transfers inva...
129
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MONET
2008
15 years 2 months ago
2008
Routers equipped with multiple 802.11 radios can alleviate capacity problems in wireless mesh networks. However, a practical, complete system architecture that can realize the bene...
118
Voted
ISCA
2010
IEEE
15 years 1 months ago
2010
IEEE
As the effective limits of frequency and instruction level parallelism have been reached, the strategy of microprocessor vendors has changed to increase the number of processing ...
151
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SIPS
2008
IEEE
15 years 9 months ago
2008
IEEE
Low-density parity-check (LDPC) codes on par with convolutional turbo codes (CTC) are two of the most powerful error correction codes known to perform very close to the Shannon li...