Sciweavers

68 search results - page 9 / 14
» Improving Memory Subsystem Performance Using ViVA: Virtual V...
Sort
View
ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
11 years 10 months ago
BlockChop: Dynamic squash elimination for hybrid processor architecture
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
Jason Mars, Naveen Kumar
ISCA
2007
IEEE
142views Hardware» more  ISCA 2007»
14 years 1 months ago
MetaTM//TxLinux: transactional memory for an operating system
This paper quantifies the effect of architectural design decisions on the performance of TxLinux. TxLinux is a Linux kernel modified to use transactions in place of locking prim...
Hany E. Ramadan, Christopher J. Rossbach, Donald E...
SIGMETRICS
2008
ACM
214views Hardware» more  SIGMETRICS 2008»
13 years 7 months ago
HMTT: a platform independent full-system memory trace monitoring system
Memory trace analysis is an important technology for architecture research, system software (i.e., OS, compiler) optimization, and application performance improvements. Many appro...
Yungang Bao, Mingyu Chen, Yuan Ruan, Li Liu, Jianp...
VEE
2010
ACM
218views Virtualization» more  VEE 2010»
14 years 2 months ago
Improving compiler-runtime separation with XIR
Intense research on virtual machines has highlighted the need for flexible software architectures that allow quick evaluation of new design and implementation techniques. The inte...
Ben Titzer, Thomas Würthinger, Doug Simon, Ma...
CASES
2007
ACM
13 years 11 months ago
A fast and generic hybrid simulation approach using C virtual machine
Instruction Set Simulators (ISSes) are important tools for cross-platform software development. The simulation speed is a major concern and many approaches have been proposed to i...
Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Asch...