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ECRTS
2008
IEEE
15 years 11 months ago
Cache-Aware Real-Time Scheduling on Multicore Platforms: Heuristics and a Case Study
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
John M. Calandrino, James H. Anderson
INFOCOM
2005
IEEE
15 years 10 months ago
Relevance of massively distributed explorations of the Internet topology: simulation results
— Internet maps are generally constructed using the traceroute tool from a few sources to many destinations. It appeared recently that this exploration process gives a partial an...
Jean-Loup Guillaume, Matthieu Latapy
SIGIR
2010
ACM
15 years 8 months ago
Blog snippets: a comments-biased approach
In the last years Blog Search has been a new exciting task in Information Retrieval. The presence of user generated information with valuable opinions makes this field of huge in...
Javier Parapar, Jorge López-Castro, Alvaro ...
TVLSI
2008
117views more  TVLSI 2008»
15 years 4 months ago
Configurable VLSI Architecture for Deblocking Filter in H.264/AVC
In this paper, we study and analyze the computational complexity of the deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. The simulation result s...
Chung-Ming Chen, Chung-Ho Chen
136
Voted
IJACTAICIT
2010
175views more  IJACTAICIT 2010»
15 years 1 months ago
Achieving CMMI Maturity Level 3 by Implementing FEAF Reference Models
The basic purpose of an Enterprise Architecture project is creating integrity among different enterprise components, including processes, systems, technologies, and etc. While CMM...
Fatemeh Kafili Kasmaee, Ramin Nassiri, Gholamreza ...