52 search results - page 4 / 11 » Improving Parallel Write by Node-Level Request Scheduling |
HPCN
1998
Springer
13 years 11 months ago
1998
Springer
We propose a tunable scheduling strategy that lies between FIFO and shortest- rst, based on the value of a coe cient Alpha. If Alpha is set to zero then this strategy is just FIFO....
HPCA
2012
IEEE
12 years 3 months ago
2012
IEEE
Main memory latencies have always been a concern for system performance. Given that reads are on the critical path for CPU progress, reads must be prioritized over writes. However...
ISCA
2008
IEEE
14 years 1 months ago
2008
IEEE
In a chip-multiprocessor (CMP) system, the DRAM system is shared among cores. In a shared DRAM system, requests from a thread can not only delay requests from other threads by cau...
ICDCS
2008
IEEE
14 years 1 months ago
2008
IEEE
This paper considers a multi-query optimization issue for distributed similarity query processing, which attempts to exploit the dependencies in the derivation of a query evaluati...
ISCA
2012
IEEE
11 years 10 months ago
2012
IEEE
Modern DRAMs have multiple banks to serve multiple memory requests in parallel. However, when two requests go to the same bank, they have to be served serially, exacerbating the h...