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» Improving Performance by Branch Reordering
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LCPC
2004
Springer
14 years 2 months ago
Branch Strategies to Optimize Decision Trees for Wide-Issue Architectures
Abstract. Branch predictors are associated with critical design issues for nowadays instruction greedy processors. We study two important domains where the optimization of decision...
Patrick Carribault, Christophe Lemuet, Jean-Thomas...
CF
2007
ACM
13 years 10 months ago
Computational and storage power optimizations for the O-GEHL branch predictor
In recent years, highly accurate branch predictors have been proposed primarily for high performance processors. Unfortunately such predictors are extremely energy consuming and i...
Kaveh Aasaraai, Amirali Baniasadi, Ehsan Atoofian
ISCA
2002
IEEE
82views Hardware» more  ISCA 2002»
14 years 1 months ago
Increasing Processor Performance by Implementing Deeper Pipelines
One architectural method for increasing processor performance involves increasing the frequency by implementing deeper pipelines. This paper will explore the relationship between ...
Eric Sprangle, Doug Carmean
ASPLOS
2009
ACM
14 years 9 months ago
Phantom-BTB: a virtualized branch target buffer design
Modern processors use branch target buffers (BTBs) to predict the target address of branches such that they can fetch ahead in the instruction stream increasing concurrency and pe...
Ioana Burcea, Andreas Moshovos
ICDE
2005
IEEE
119views Database» more  ICDE 2005»
14 years 10 months ago
Batched Processing for Information Filters
This paper describes batching, a novel technique in order to improve the throughput of an information filter (e.g. message broker or publish & subscribe system). Rather than p...
Peter M. Fischer, Donald Kossmann