315 search results - page 28 / 63 » Improving Performance by Branch Reordering |
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
—With the advancement of CMOS manufacturing process to nano-scale, future shipped microprocessors will be increasingly vulnerable to intermittent faults. Quantitatively character...
CODES
2000
IEEE
14 years 1 months ago
2000
IEEE
Memory interleaving is a cost-efficient approach to increase bandwidth. Improving data access locality and reducing memory access conflicts are two important aspects to achieve hi...
SIGGRAPH
1999
ACM
14 years 1 months ago
1999
ACM
Bus traffic between the graphics subsystem and memory can become a bottleneck when rendering geometrically complex meshes. In this paper, we investigate the use of vertex caching...
ISCA
2012
IEEE
11 years 11 months ago
2012
IEEE
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...
CVPR
2007
IEEE
14 years 10 months ago
2007
IEEE
We look at the problem of location recognition in a large image dataset using a vocabulary tree. This entails finding the location of a query image in a large dataset containing 3...