328 search results - page 25 / 66 » Improving Performance of Small On-Chip Instruction Caches |
ADHOC
2007
13 years 7 months ago
2007
Wireless mesh networks (WMNs) have been proposed to provide cheap, easily deployable and robust Internet access. The dominant Internet-access traffic from clients causes a congest...
MICRO
2008
IEEE
14 years 2 months ago
2008
IEEE
It is well recognized that LRU cache-line replacement can be ineffective for applications with large working sets or non-localized memory access patterns. Specifically, in lastle...
IISWC
2006
IEEE
14 years 1 months ago
2006
IEEE
The load instructions of some of the bioinformatics applications in the BioPerf suite possess interesting characteristics: only a few static loads cover almost the entire dynamic ...
VLDB
2005
ACM
14 years 1 months ago
2005
ACM
Simultaneous multithreading (SMT) allows multiple threads to supply instructions to the instruction pipeline of a superscalar processor. Because threads share processor resources,...
LCTRTS
2005
Springer
14 years 1 months ago
2005
Springer
Effective use of the memory hierarchy is critical for achieving high performance on embedded systems. We focus on the class of streaming applications, which is increasingly preval...