328 search results - page 34 / 66 » Improving Performance of Small On-Chip Instruction Caches |
SIGMETRICS
1997
ACM
13 years 11 months ago
1997
ACM
In this paper we present a performance study of memory reference behavior in network protocol processing, using an Internet-based protocol stack implemented in the x-kernel runnin...
OSDI
2004
ACM
14 years 7 months ago
2004
ACM
Program-counter-based (PC-based) prediction techniques have been shown to be highly effective and are widely used in computer architecture design. In this paper, we explore the op...
IEEEPACT
2006
IEEE
14 years 1 months ago
2006
IEEE
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
IPCCC
1999
IEEE
13 years 12 months ago
1999
IEEE
Performance of Web servers is critical to the success of many corporations and organizations. However, very few results have been published that quantitatively study the server be...
PLDI
2005
ACM
14 years 1 months ago
2005
ACM
This paper describes Automatic Pool Allocation, a transformation framework that segregates distinct instances of heap-based data structures into seperate memory pools and allows h...