328 search results - page 39 / 66 » Improving Performance of Small On-Chip Instruction Caches |
ISPASS
2007
IEEE
14 years 1 months ago
2007
IEEE
We have studied DRAM-level prefetching for the fully buffered DIMM (FB-DIMM) designed for multi-core processors. FB-DIMM has a unique two-level interconnect structure, with FB-DIM...
HIPEAC
2009
Springer
14 years 5 days ago
2009
Springer
Abstract. Technological advances and increasingly complex and dynamic application behavior argue for revisiting mechanisms that adapt logical cache block size to application charac...
MICRO
1998
IEEE
13 years 11 months ago
1998
IEEE
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
ISCA
2000
IEEE
13 years 12 months ago
2000
IEEE
This paper evaluates performance characteristics of the Compaq ES40 shared memory multiprocessor. The ES40 system contains up to four Alpha 21264 CPU’s together with a high-perf...
CCGRID
2010
IEEE
13 years 6 months ago
2010
IEEE
—While computing speed continues increasing rapidly, data-access technology is lagging behind. Data-access delay, not the processor speed, becomes the leading performance bottlen...