328 search results - page 52 / 66 » Improving Performance of Small On-Chip Instruction Caches |
VLDB
2005
ACM
14 years 29 days ago
2005
ACM
In this paper, we examine the performance of frequent pattern mining algorithms on a modern processor. A detailed performance study reveals that even the best frequent pattern min...
ICPP
2005
IEEE
14 years 1 months ago
2005
IEEE
Java-based middleware is a rapidly growing workload for high-end server processors, particularly Chip Multiprocessors (CMP). To help architects design future microprocessors to ru...
IEEEPACT
2009
IEEE
14 years 2 months ago
2009
IEEE
—CPR (Checkpoint Processing and Recovery) is a physical register management scheme that supports a larger instruction window and higher average IPC than conventional ROB-style re...
CGO
2006
IEEE
14 years 1 months ago
2006
IEEE
Software prefetching has been demonstrated as a powerful technique to tolerate long load latencies. However, to be effective, prefetching must target the most critical (frequently...
APCSAC
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract. Bypass delays are expected to grow beyond 1ns as technology scales. These delays necessitate pipelining of bypass paths at processor frequencies above 1GHz and thus affe...