Sciweavers

1045 search results - page 102 / 209
» Improving SHA-2 Hardware Implementations
Sort
View
IJSNET
2006
133views more  IJSNET 2006»
13 years 10 months ago
On the hop count statistics for randomly deployed wireless sensor networks
: In this paper we focus on exploiting the information provided by a generally accepted and largely ignored hypothesis (the random deployment of the nodes of an ad hoc or wireless ...
Stefan Dulman, Michele Rossi, Paul J. M. Havinga, ...
STTT
2010
115views more  STTT 2010»
13 years 8 months ago
Scalable shared memory LTL model checking
Recent development in computer hardware has brought more wide-spread emergence of shared memory, multi-core systems. These architectures offer opportunities to speed up various ta...
Jiri Barnat, Lubos Brim, Petr Rockai
ICIP
2004
IEEE
14 years 11 months ago
Deringing and deblocking dct compression artifacts with efficient shifted transforms
A new method, using weighted combinations of shifted transforms, is developed for deringing and deblocking DCT compressed color images. The method shows substantial deringing impr...
Ramin Samadani, Arvind Sundararajan, Amir Said
PDCAT
2007
Springer
14 years 4 months ago
High Throughput Multi-port MT19937 Uniform Random Number Generator
ct There have been many previous attempts to accelerate MT19937 using FPGAs but we believe that we can substantially improve the previous implementations to develop a higher throug...
Vinay Sriram, David Kearney
APCSAC
2003
IEEE
14 years 3 months ago
Arithmetic Circuits Combining Residue and Signed-Digit Representations
This paper discusses the use of signed-digit representations in the implementation of fast and efficient residue-arithmetic units. Improvements to existing signed-digit modulo adde...
Anders Lindström, Michael Nordseth, Lars Beng...