1045 search results - page 111 / 209 » Improving SHA-2 Hardware Implementations |
MICRO
1997
IEEE
14 years 2 months ago
1997
IEEE
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occu...
CSB
2004
IEEE
14 years 1 months ago
2004
IEEE
Our previous work to accelerate phylogeny inference using HW/SW(Hardware/Software) co-design has recently been extended to a more powerful embedded computing platform. In this pla...
ATS
2001
IEEE
14 years 1 months ago
2001
IEEE
Test access is a major problem for core-based systemon-chip (SOC) designs. Since cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms...
ASAP
2007
IEEE
13 years 12 months ago
2007
IEEE
Network processors utilizing general-purpose instruction-set architectures (ISA) limit network throughput due to latency incurred from cryptography and hashing applications (AES, ...
SPAA
2009
ACM
14 years 10 months ago
2009
ACM
This workshop paper reports work in progress on NZTM, a nonblocking, zero-indirection object-based hybrid transactional memory system. NZTM can execute transactions using best-eff...