1045 search results - page 147 / 209 » Improving SHA-2 Hardware Implementations |
FPGA
2005
ACM
14 years 1 months ago
2005
ACM
Floating-point Sparse Matrix-Vector Multiplication (SpMXV) is a key computational kernel in scientific and engineering applications. The poor data locality of sparse matrices sig...
RT
2001
Springer
14 years 3 days ago
2001
Springer
This paper presents a technique for representing and displaying high dynamic-range texture maps (HDRTMs) using current graphics hardware. Dynamic range in real-world environments o...
ISCA
1997
IEEE
13 years 12 months ago
1997
IEEE
Recent technological advances have produced network interfaces that provide users with very low-latency access to the memory of remote machines. We examine the impact of such netw...
HPDC
2010
IEEE
2010
IEEE
XCo: explicit coordination to prevent network fabric congestion in cloud computing cluster platforms
13 years 8 months ago
Large cluster-based cloud computing platforms increasingly use commodity Ethernet technologies, such as Gigabit Ethernet, 10GigE, and Fibre Channel over Ethernet (FCoE), for intra...
SIGMETRICS
2008
ACM
13 years 7 months ago
2008
ACM
Memory trace analysis is an important technology for architecture research, system software (i.e., OS, compiler) optimization, and application performance improvements. Many appro...