Sciweavers

1045 search results - page 17 / 209
» Improving SHA-2 Hardware Implementations
Sort
View
FCCM
2009
IEEE
169views VLSI» more  FCCM 2009»
14 years 3 months ago
RC-BLASTn: Implementation and Evaluation of the BLASTn Scan Function
BLASTn is a tool universally used by biologists to identify similarities between nucleotide based biological genome sequences. This report describes an FPGA based hardware impleme...
Siddhartha Datta, Parag Beeraka, Ron Sass
ITCC
2005
IEEE
14 years 2 months ago
FPGA Implementations of the ICEBERG Block Cipher
— This paper presents FPGA (Field Programmable Gate Array) implementations of ICEBERG, a block cipher designed for reconfigurable hardware implementations and presented at FSE 2...
François-Xavier Standaert, Gilles Piret, Ga...
IAJIT
2010
140views more  IAJIT 2010»
13 years 7 months ago
HW/SW Design-Based Implementation of Vector Median Rational Hybrid Filter
: A new code sign implementation of vector median rational hybrid filter based on efficient hardware/software implementation is introduced and applied to colour image filtering pro...
Anis Boudabous, Ahmed Ben Atitallah, Lazhar Khriji...
EUROPAR
2003
Springer
14 years 1 months ago
Implementation and Performance Evaluation of M-VIA on AceNIC Gigabit Ethernet Card
This paper describes the implementation and performance of M-VIA on the AceNIC Gigabit Ethernet card. The AceNIC adapter has several notable hardware features for high-speed commun...
In-Su Yoon, Sang-Hwa Chung, Ben Lee, Hyuk-Chul Kwo...
WSCG
2004
161views more  WSCG 2004»
13 years 10 months ago
Rendering Techniques for Hardware-Accelerated Image-Based CSG
Image-based CSG rendering algorithms for standard graphics hardware rely on multipass rendering that includes reading and writing large amounts of pixel data from and to the frame...
Florian Kirsch, Jürgen Döllner