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» Improving SHA-2 Hardware Implementations
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ISCA
1997
IEEE
96views Hardware» more  ISCA 1997»
14 years 2 months ago
DataScalar Architectures
DataScalar architectures improve memory system performance by running computation redundantly across multiple processors, which are each tightly coupled with an associated memory....
Doug Burger, Stefanos Kaxiras, James R. Goodman
ICCD
2004
IEEE
131views Hardware» more  ICCD 2004»
14 years 6 months ago
3D Processing Technology and Its Impact on iA32 Microprocessors
This short paper explores an implementation of a new technology called 3D die stacking and describes research activity at Intel. 3D die stacking is the bonding of two die either f...
Bryan Black, Donald Nelson, Clair Webb, Nick Samra
ICCD
2006
IEEE
132views Hardware» more  ICCD 2006»
14 years 6 months ago
FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems
— High secure cryptographic systems require large bit-length encryption keys which presents a challenge to their efficient hardware implementation especially in embedded devices...
Osama Al-Khaleel, Christos A. Papachristou, Franci...
GLVLSI
2006
IEEE
126views VLSI» more  GLVLSI 2006»
14 years 4 months ago
Hardware/software partitioning of operating systems: a behavioral synthesis approach
In this paper we propose a hardware real time operating system (HW-RTOS) solution that makes use of a dedicated hardware in order to replace the standard support provided by the P...
Sathish Chandra, Francesco Regazzoni, Marcello Laj...
SIGCOMM
1995
ACM
14 years 1 months ago
Performance Analysis of MD5
MD5 is an authentication algorithm proposed as the required implementation of the authentication option in IPv6. This paper presents an analysis of the speed at which MD5 can be i...
Joseph D. Touch