5523 search results - page 26 / 1105 » Improving application performance with hardware data structu... |
IPPS
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
CAIP
1997
Springer
13 years 11 months ago
1997
Springer
: A new hardware structure for implementation of soft morphological filters is presented in this paper. This is based on the modification of the majority gate technique. A pipeline...
GLOBECOM
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract−Several high performance LDPC codes have paritycheck matrices composed of permutation submatrices. We design a parallel-serial architecture to map the decoder of any str...
VLSISP
2008
13 years 7 months ago
2008
The speedups and the energy reductions achieved in a generic single-chip microprocessor system by employing a high-performance data-path are presented. The data-path acts as a copr...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper, we present performance results from mapping five real-world DSP applications on an embedded system-on-chip that incorporates coarse-grain reconfigurable logic with ...