Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware

In this paper, we present performance results from mapping five real-world DSP applications on an embedded system-on-chip that incorporates coarse-grain reconfigurable logic with an instruction-set processor. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elements. A mapping flow for improving application’s performance by accelerating critical software parts, called kernels, on the CoarseGrain Reconfigurable Array is proposed. Profiling is performed for detecting critical kernel code. For mapping the detected kernels on the reconfigurable logic a priority-based mapping algorithm has been developed. The experiments for three different instances of a generic system show that the speedup from executing kernels on

• Type: Conference
• Year: 2006
• Where: IPPS
• Authors: Michalis D. Galanis, Grigoris Dimitroulakos, Constantinos E. Goutis
• Keywords: Coarse-grain Reconfigurable Logic, CoarseGrain Reconfigurable Array, Distributed And Parallel Computing, IPPS 2006, Reconfigurable Logic