71 search results - page 11 / 15 » Improving memory bank-level parallelism in the presence of p... |
IEEEPACT
2006
IEEE
14 years 1 months ago
2006
IEEE
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
SIGMETRICS
1992
ACM
13 years 11 months ago
1992
ACM
To cope with the increasing difference between processor and main memory speeds, modern computer systems use deep memory hierarchies. In the presence of such hierarchies, the perf...
HPCA
2005
IEEE
14 years 7 months ago
2005
IEEE
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
IEEEPACT
2006
IEEE
14 years 1 months ago
2006
IEEE
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...
ISORC
2002
IEEE
14 years 8 days ago
2002
IEEE
The demand for real-time database services has been increasing recently. Examples include sensor data fusion, stock trading, decision support, web information services, and data-i...