71 search results - page 4 / 15 » Improving memory bank-level parallelism in the presence of p... |
JSSPP
2000
Springer
13 years 11 months ago
2000
Springer
Abstract. Buffered coscheduling is a new methodology that can substantially increase resource utilization, improve response time, and simplify the development of the run-time suppo...
PPOPP
2009
ACM
14 years 8 months ago
2009
ACM
Data prefetching has been widely used in the past as a technique for hiding memory access latencies. However, data prefetching in multi-threaded applications running on chip multi...
ASPLOS
2011
ACM
12 years 11 months ago
2011
ACM
Multicore processors have become ubiquitous in today’s systems, but exploiting the parallelism they offer remains difficult, especially for legacy application and applications ...
ICDCS
2007
IEEE
14 years 1 months ago
2007
IEEE
State-of-the-art networked storage servers are equipped with increasingly powerful computing capability and large DRAM memory as storage caches. However, their contribution to the...
ICPP
2003
IEEE
14 years 19 days ago
2003
IEEE
Aggressive hardware-based and software-based prefetch algorithms for hiding memory access latencies were proposed to bridge the gap of the expanding speed disparity between proces...