Sciweavers

1001 search results - page 173 / 201
» Improving memory hierarchy performance for irregular applica...
Sort
View
DSD
2008
IEEE
139views Hardware» more  DSD 2008»
14 years 12 days ago
Revisiting the Cache Effect on Multicore Multithreaded Network Processors
Caching mechanism has achieved great success in general purpose processor; however, its deployment in Network Processor (NP) raises questions over its effectiveness under the new ...
Zhen Liu, Jia Yu, Xiaojun Wang, Bin Liu, Laxmi N. ...
GECCO
2007
Springer
159views Optimization» more  GECCO 2007»
14 years 4 months ago
Evolutionary hypernetwork models for aptamer-based cardiovascular disease diagnosis
We present a biology-inspired probabilistic graphical model, called the hypernetwork model, and its application to medical diagnosis of disease. The hypernetwork models are a way ...
JungWoo Ha, Jae-Hong Eom, Sung-Chun Kim, Byoung-Ta...
CODES
2004
IEEE
14 years 2 months ago
A loop accelerator for low power embedded VLIW processors
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
Binu K. Mathew, Al Davis
PLDI
2011
ACM
13 years 1 months ago
A case for an SC-preserving compiler
The most intuitive memory consistency model for shared-memory multi-threaded programming is sequential consistency (SC). However, current concurrent programming languages support ...
Daniel Marino, Abhayendra Singh, Todd D. Millstein...
IEEEPACT
2006
IEEE
14 years 4 months ago
Region array SSA
Static Single Assignment (SSA) has become the intermediate program representation of choice in most modern compilers because it enables efficient data flow analysis of scalars an...
Silvius Rus, Guobin He, Christophe Alias, Lawrence...