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FPL
2008
Springer
143views Hardware» more  FPL 2008»
13 years 9 months ago
Fast toggle rate computation for FPGA circuits
This paper presents a fast and scalable method of computing signal toggle rate in FPGA-based circuits. Our technique is a vectorless estimation technique, which can be used in a C...
Tomasz S. Czajkowski, Stephen Dean Brown
CCGRID
2010
IEEE
13 years 6 months ago
An Adaptive Data Prefetcher for High-Performance Processors
—While computing speed continues increasing rapidly, data-access technology is lagging behind. Data-access delay, not the processor speed, becomes the leading performance bottlen...
Yong Chen, Huaiyu Zhu, Xian-He Sun
VLSID
2010
IEEE
170views VLSI» more  VLSID 2010»
13 years 1 months ago
Novel Vth Hopping Techniques for Aggressive Runtime Leakage Contro
The continuous increase of leakage power consumption in deep sub-micro technologies necessitates more aggressive leakage control. Runtime leakage control (RTLC) is effective, si...
Hao Xu, Wen-Ben Jone, Ranga Vemuri
CISS
2010
IEEE
12 years 11 months ago
Queue based compression in a two-way relay network
—We consider the problem of joint rate scheduling and lossy data compression in a two-way relay network with distortion-sensitive stochastic packet traffic. A relay node facilit...
Ertugrul Necdet Ciftcioglu, Yalin Evren Sagduyu, A...
DAC
2000
ACM
14 years 8 months ago
Memory aware compilation through accurate timing extraction
Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode) partly alleviate this ...
Peter Grun, Nikil D. Dutt, Alexandru Nicolau