This paper presents a fast and scalable method of computing signal toggle rate in FPGA-based circuits. Our technique is a vectorless estimation technique, which can be used in a C...
—While computing speed continues increasing rapidly, data-access technology is lagging behind. Data-access delay, not the processor speed, becomes the leading performance bottlen...
The continuous increase of leakage power consumption
in deep sub-micro technologies necessitates more aggressive
leakage control. Runtime leakage control (RTLC) is effective,
si...
—We consider the problem of joint rate scheduling and lossy data compression in a two-way relay network with distortion-sensitive stochastic packet traffic. A relay node facilit...
Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode) partly alleviate this ...