Sciweavers

271 search results - page 47 / 55
» Improving the Average Delay of Sorting
Sort
View
ISCA
2011
IEEE
386views Hardware» more  ISCA 2011»
14 years 9 months ago
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xi...
EUROSYS
2011
ACM
14 years 9 months ago
Is co-scheduling too expensive for SMP VMs?
Symmetric multiprocessing (SMP) virtual machines (VMs) allow users to take advantage of a multiprocessor infrastructure. Despite the advantage, SMP VMs can cause synchronization l...
Orathai Sukwong, Hyong S. Kim
IEEEPACT
2006
IEEE
15 years 12 months ago
Overlapping dependent loads with addressless preload
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
Zhen Yang, Xudong Shi, Feiqi Su, Jih-Kwon Peir
MOBICOM
2006
ACM
15 years 12 months ago
Experimental evaluation and characterization of the magnets wireless backbone
High-speed wireless backbones have the potential to replace or complement wired connections. This paper provides a comprehensive network and transport layer performance evaluation...
Roger Karrer, Istvan Matyasovszki, Alessio Botta, ...
IEICET
2008
106views more  IEICET 2008»
15 years 6 months ago
Realization of Low Power High-Speed Channel Filters with Stringent Adjacent Channel Attenuation Specifications for Wireless Comm
Finite impulse response (FIR) filtering is the most computationally intensive operation in the channelizer of a wireless communication receiver. Higher order FIR channel filters a...
Jimson Mathew, R. Mahesh, A. Prasad Vinod, Edmund ...