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GLVLSI
2008
IEEE
112views VLSI» more  GLVLSI 2008»
14 years 4 months ago
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells
Share of leakage in cache memories is increasing with technology scaling. Studies show that most stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which...
Maziar Goudarzi, Tohru Ishihara
KDD
2009
ACM
245views Data Mining» more  KDD 2009»
14 years 10 months ago
Mining rich session context to improve web search
User browsing information, particularly their non-search related activity, reveals important contextual information on the preferences and the intent of web users. In this paper, ...
Guangyu Zhu, Gilad Mishne
WWW
2005
ACM
14 years 3 months ago
Improved timing control for web server systems using internal state information
How to effectively allocate system resource to meet the Service Level Agreement (SLA) of Web servers is a challenging problem. In this paper, we propose an improved scheme for aut...
Xue Liu, Rong Zheng, Jin Heo, Lui Sha
ASSETS
2007
ACM
14 years 1 months ago
SADIe: exposing implicit information to improve accessibility
The World Wide Web (Web) is a visually complex, multimedia system that can be inaccessible to people with visual impairments. SADIe addresses this problem by using Semantic Web te...
Darren Lunn
ISCA
1993
IEEE
153views Hardware» more  ISCA 1993»
14 years 2 months ago
An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing
Parallel programs that use critical sections and are executed on a shared-memory multiprocessor with a writeinvalidate protocol result in invalidation actions that could be elimin...
Per Stenström, Mats Brorsson, Lars Sandberg