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CASES
2001
ACM
14 years 1 months ago
Combined partitioning and data padding for scheduling multiple loop nests
With the widening performance gap between processors and main memory, efficient memory accessing behavior is necessary for good program performance. Loop partition is an effective...
Zhong Wang, Edwin Hsing-Mean Sha, Xiaobo Hu
RTSS
2003
IEEE
14 years 3 months ago
Experimental Evaluation of Code Properties for WCET Analysis
This paper presents a quantification of the timing effects that advanced processor features like data and instruction cache, pipelines, branch prediction units and out-oforder ex...
Antoine Colin, Stefan M. Petters
CCGRID
2002
IEEE
14 years 3 months ago
Tracing a Large-Scale Peer to Peer System: An Hour in the Life of Gnutella
Peer-to-peer computing and networking, an emerging model of communication and computation, has recently started to gain significant acceptance. This model not only enables client...
Evangelos P. Markatos
HPCA
2000
IEEE
14 years 2 months ago
Design of a Parallel Vector Access Unit for SDRAM Memory Systems
We are attacking the memory bottleneck by building a “smart” memory controller that improves effective memory bandwidth, bus utilization, and cache efficiency by letting appl...
Binu K. Mathew, Sally A. McKee, John B. Carter, Al...
CASES
2001
ACM
14 years 1 months ago
Heads and tails: a variable-length instruction format supporting parallel fetch and decode
Abstract. Existing variable-length instruction formats provide higher code densities than fixed-length formats, but are ill-suited to pipelined or parallel instruction fetch and de...
Heidi Pan, Krste Asanovic