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ISCA
1996
IEEE
99views Hardware» more  ISCA 1996»
13 years 11 months ago
Performance Comparison of ILP Machines with Cycle Time Evaluation
Many studies have investigated performance improvement through exploiting instruction-level parallelism (ILP) with a particular architecture. Unfortunately, these studies indicate...
Tetsuya Hara, Hideki Ando, Chikako Nakanishi, Masa...
DEXA
2009
Springer
138views Database» more  DEXA 2009»
14 years 1 months ago
Evaluating Non-In-Place Update Techniques for Flash-Based Transaction Processing Systems
Recently, flash memory is emerging as the storage device. With price sliding fast, the cost per capacity is approaching to that of SATA disk drives. So far flash memory has been ...
Yongkun Wang, Kazuo Goda, Masaru Kitsuregawa
ISCA
2002
IEEE
103views Hardware» more  ISCA 2002»
13 years 12 months ago
Efficient Dynamic Scheduling Through Tag Elimination
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...
Dan Ernst, Todd M. Austin
ICPADS
2005
IEEE
14 years 20 days ago
A Pure Lazy Technique for Scalable Transaction Processing in Replicated Databases
Recently, there have been proposals for scaling-up a database system using lazy replication. In these proposals, system scale-up is achieved through the addition of secondary site...
Khuzaima Daudjee, Kenneth Salem
LCTRTS
2009
Springer
14 years 1 months ago
Debugging FPGA-based packet processing systems through transaction-level communication-centric monitoring
The fine-grained parallelism inherent in FPGAs has encouraged their use in packet processing systems. Debugging and performance evaluation of such complex designs can be signifi...
Paul Edward McKechnie, Michaela Blott, Wim Vanderb...