24 search results - page 3 / 5 » Improving the Throughput of a Pipeline by Insertion of Delay... |
TAMC
2007
Springer
14 years 2 months ago
2007
Springer
In previous work we have introduced an average-case measure for the time complexity of Boolean circuits – that is the delay between feeding the input bits into a circuit and the ...
ICCAD
2008
IEEE
14 years 5 months ago
2008
IEEE
— This paper presents a fast analytical method for estimating the throughput of pipelined asynchronous systems, and then applies that method to develop a fast solution to the pro...
IPPS
2008
IEEE
14 years 2 months ago
2008
IEEE
Pipelined SRAM-based algorithmic solutions have become competitive alternatives to TCAMs (ternary content addressable memories) for high throughput IP lookup. Multiple pipelines c...
APCSAC
2006
IEEE
14 years 2 months ago
2006
IEEE
Abstract. Bypass delays are expected to grow beyond 1ns as technology scales. These delays necessitate pipelining of bypass paths at processor frequencies above 1GHz and thus affe...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
Since across-chip interconnect delays can exceed a clock cycle in nanometer technologies, it has become essential in high performance designs to add flip-flops on wires with multi...