309 search results - page 22 / 62 » In-Network Cache Coherence |
SBCCI
2009
ACM
14 years 2 months ago
2009
ACM
We present an application-driven customization methodology for energy-efficient inter-core communication in embedded multiprocessors. The methodology leverages configurable cach...
APPT
2009
Springer
13 years 11 months ago
2009
Springer
Abstract. In many-core CMP architectures, the cache coherence protocol is a key component since it can add requirements of area and power consumption to the final design and, there...
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
With transistor miniaturization leading to an abundance of on-chip resources and uniprocessor designs providing diminishing returns, the industry has moved beyond single-core micr...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
DSL
1997
13 years 9 months ago
1997
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cache coherence protocols. Cache coherence is of concern when parallel and distrib...