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MICRO
2007
IEEE
94views Hardware» more  MICRO 2007»
14 years 1 months ago
Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors
Snoopy cache coherence can be implemented in any physical network topology by embedding a logical unidirectional ring in the network. Control messages are forwarded using the ring...
Karin Strauss, Xiaowei Shen, Josep Torrellas
BIRTHDAY
2009
Springer
14 years 8 days ago
Pervasive Theory of Memory
For many aspects of memory theoretical treatment already exists, in particular for: simple cache construction, store buers and store buer forwarding, cache coherence protocols, o...
Ulan Degenbaev, Wolfgang J. Paul, Norbert Schirmer
ASPLOS
2008
ACM
13 years 9 months ago
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...
Chinnakrishnan S. Ballapuram, Ahmad Sharif, Hsien-...
ICS
2010
Tsinghua U.
14 years 5 months ago
Cache Replacement Policies for Multicore Processors
Almost all of the modern computers use multiple cores, and the number of cores is expected to increase as hardware prices go down, and Moore's law fails to hold. Most of the ...
Avinatan Hassidim
MAM
2002
151views more  MAM 2002»
13 years 7 months ago
A performance evaluation of cache injection in bus-based shared memory multiprocessors
Bus-based shared memory multiprocessors with private caches and snooping write-invalidate cache coherence protocols are dominant form of small- to medium-scale parallel machines t...
Aleksandar Milenkovic, Veljko M. Milutinovic