309 search results - page 56 / 62 » In-Network Cache Coherence |
HPCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Most shared memory systems maximize performance by unpredictably resolving memory races. Unpredictable memory races can lead to nondeterminism in parallel programs, which can suff...
ISCA
2000
IEEE
13 years 12 months ago
2000
IEEE
Communication in cache-coherent distributed shared memory (DSM) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. This paper...
HPCA
1998
IEEE
13 years 12 months ago
1998
IEEE
The explosive growth in the performance of microprocessors and networks has created a new opportunity to reduce the latency of fine-grain communication. Microprocessor clock speed...
SC
1995
ACM
13 years 11 months ago
1995
ACM
The goal of this work is to explore architectural mechanisms for supporting explicit communication in cachecoherent shared memory multiprocessors. The motivation stems from the ob...
OOPSLA
2010
Springer
13 years 6 months ago
2010
Springer
Heterogeneous multi-core processors, such as the IBM Cell processor, can deliver high performance. However, these processors are notoriously difficult to program: different cores...