661 search results - page 117 / 133 » Increasing Processor Performance by Implementing Deeper Pipe... |
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional un...
Publication
Continuing improvements in CPU and GPU performances as well as increasing multi-core processor and cluster-based parallelism demand for flexible and scalable parallel rendering sol...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
Snoopy cache coherence protocols broadcast requests to all nodes, reducing the latency of cache to cache transfer misses at the expense of increasing interconnect power. We propos...
SC
1991
ACM
13 years 11 months ago
1991
ACM
In cache based multiprocessors a protocol must maintain coherence among replicated copies of shared writable data. In delayed consistency protocols the effect of out-going and in-...
BMCBI
2010
13 years 7 months ago
2010
Background: In recent years, the demand for computational power in computational biology has increased due to rapidly growing data sets from microarray and other high-throughput t...