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MICRO
1997
IEEE
90views Hardware» more  MICRO 1997»
13 years 11 months ago
ProfileMe: Hardware Support for Instruction-Level Profiling on Out-of-Order Processors
Profile data is valuable for identifying performance bottlenecks and guiding optimizations. Periodic sampling of a processor's performance monitoring hardware is an effective...
Jeffrey Dean, James E. Hicks, Carl A. Waldspurger,...
ICS
2005
Tsinghua U.
14 years 26 days ago
Reducing latencies of pipelined cache accesses through set prediction
With the increasing performance gap between the processor and the memory, the importance of caches is increasing for high performance processors. However, with reducing feature si...
Aneesh Aggarwal
ASPDAC
2004
ACM
75views Hardware» more  ASPDAC 2004»
14 years 24 days ago
Power-performance trade-off using pipeline delays
— We study the delays faced by instructions in the pipeline of a superscalar processor and its impact on power and performance. Instructions that are ready-on-dispatch (ROD) are ...
G. Surendra, Subhasis Banerjee, S. K. Nandy
ISCA
2009
IEEE
161views Hardware» more  ISCA 2009»
14 years 2 months ago
AnySP: anytime anywhere anyway signal processing
In the past decade, the proliferation of mobile devices has increased at a spectacular rate. There are now more than 3.3 billion active cell phones in the world—a device that we...
Mark Woh, Sangwon Seo, Scott A. Mahlke, Trevor N. ...
ICDE
2009
IEEE
150views Database» more  ICDE 2009»
14 years 9 months ago
Oracle Streams: A High Performance Implementation for Near Real Time Asynchronous Replication
We present the architectural design and recent performance optimizations of a state of the art commercial database replication technology provided in Oracle Streams. The underlying...
Lik Wong, Nimar S. Arora, Lei Gao, Thuvan Hoang, J...