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PPL
2008
63views more  PPL 2008»
13 years 7 months ago
Using Hardware Multithreading to Overcome Broadcast/Reduction Latency in an Associative SIMD Processor
The latency of broadcast/reduction operations has a significant impact on the performance of SIMD processors. This is especially true for associative programs, which make extensiv...
Kevin Schaffer, Robert A. Walker
FPL
2009
Springer
161views Hardware» more  FPL 2009»
14 years 11 hour ago
A multi-FPGA architecture for stochastic Restricted Boltzmann Machines
Although there are many neural network FPGA architectures, there is no framework for designing large, high-performance neural networks suitable for the real world. In this paper, ...
Daniel L. Ly, Paul Chow
WWW
2005
ACM
14 years 8 months ago
A multi-threaded PIPELINED Web server architecture for SMP/SoC machines
Design of high performance Web servers has become a recent research thrust to meet the increasing demand of networkbased services. In this paper, we propose a new Web server archi...
Gyu Sang Choi, Jin-Ha Kim, Deniz Ersoz, Chita R. D...
ASPDAC
2005
ACM
100views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Microarchitecture evaluation with floorplanning and interconnect pipelining
— As microprocessor technology continues to scale into the nanometer regime, recent studies show that interconnect delay will be a limiting factor for performance, and multiple c...
Ashok Jagannathan, Hannah Honghua Yang, Kris Konig...
ICASSP
2011
IEEE
12 years 11 months ago
Energy-optimized high performance FFT processor
This paper proposes an ultra low energy FFT processor suitable for sensor applications. The processor is based on R4MDC but achieves full utilization of computational elements. It...
Dongsuk Jeon, Mingoo Seok, Chaitali Chakrabarti, D...