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ISSS
1997
IEEE
83views Hardware» more  ISSS 1997»
13 years 11 months ago
A Scheduling and Pipelining Algorithm for Hardware/Software Systems
Given a hardware/software partitioned specification and an allocation (number and type) of processors, we present an algorithm to (1) map each of the software behaviors (or tasks...
Smita Bakshi, Daniel Gajski
CF
2007
ACM
13 years 11 months ago
By-passing the out-of-order execution pipeline to increase energy-efficiency
Out-of-order execution significantly increases the performance of superscalar processors. The out-of-order execution mechanism is, however, energy-inefficient, which inhibits scal...
Hans Vandierendonck, Philippe Manet, Thibault Dela...
HPCA
2012
IEEE
12 years 2 months ago
Power balanced pipelines
Since the onset of pipelined processors, balancing the delay of the microarchitectural pipeline stages such that each microarchitectural pipeline stage has an equal delay has been...
John Sartori, Ben Ahrens, Rakesh Kumar
SBACPAD
2006
IEEE
147views Hardware» more  SBACPAD 2006»
14 years 1 months ago
Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors
Neural-inspired branch predictors achieve very low branch misprediction rates. However, previously proposed implementations have a variety of characteristics that make them challe...
Daniel A. Jiménez, Gabriel H. Loh
ARC
2009
Springer
241views Hardware» more  ARC 2009»
14 years 2 months ago
Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm
As the need for information security increases in our everyday life, the job of encoding/decoding for secure information delivery becomes a critical issue in data network systems. ...
Jaeyoung Yi, Karam Park, Joonseok Park, Won Woo Ro