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ISCA
2002
IEEE
14 years 1 months ago
2002
IEEE
The number of pipeline stages separating dynamic instruction scheduling from instruction execution has increased considerably in recent out-of-order microprocessor implementations...
ISCA
1997
IEEE
14 years 22 days ago
1997
IEEE
The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, ...
CF
2007
ACM
2007
ACM
Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors
14 years 15 days ago
Energy-efficient microprocessor designs are one of the major concerns in both high performance and embedded processor domains. Furthermore, as process technology advances toward d...
MICRO
1994
IEEE
14 years 19 days ago
1994
IEEE
High performance architectures have always had to deal with the performance-limiting impact of branch operations. Microprocessor designs are going to have to deal with this proble...
ASPLOS
2009
ACM
14 years 9 months ago
2009
ACM
Parallel bit stream algorithms exploit the SWAR (SIMD within a register) capabilities of commodity processors in high-performance text processing applications such as UTF8 to UTF-...