661 search results - page 5 / 133 » Increasing Processor Performance by Implementing Deeper Pipe... |
EURODAC
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper proposes a new method to design an optimal instruction set for pipelined ASIP development using a formal HW/SW codesign methodology. The codesign task addressed in this...
MICRO
2005
IEEE
14 years 28 days ago
2005
IEEE
Until recently, a steadily rising clock rate and other uniprocessor microarchitectural improvements could be relied upon to consistently deliver increasing performance for a wide ...
VLSI
2010
Springer
13 years 5 months ago
2010
Springer
—Latency insensitivity is a promising design paradigm in the nanometer era since it has potential benefits of increased modularity and robustness to variations. Synchronous elas...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
Multiprocessor SoC systems have led to the increasing use of parallel hardware along with the associated software. These approaches have included coprocessor, homogeneous processo...
PLDI
2005
ACM
14 years 27 days ago
2005
ACM
Code placement techniques have traditionally improved instruction fetch bandwidth by increasing instruction locality and decreasing the number of taken branches. However, traditio...