Automatic Thread Extraction with Decoupled Software Pipelining

Until recently, a steadily rising clock rate and other uniprocessor microarchitectural improvements could be relied upon to consistently deliver increasing performance for a wide range of applications. Current difficulties in maintaining this trend have lead microprocessor manufacturers to add value by incorporating multiple processors on a chip. Unfortunately, since decades of compiler research have not succeeded in delivering automatic threading for prevalent code properties, this approach demonstrates no improvement for a large class of existing codes. To find useful work for chip multiprocessors, we propose an automatic approach to thread extraction, called Decoupled Software Pipelining (DSWP). DSWP exploits the finegrained pipeline parallelism lurking in most applications to extract long-running, concurrently executing threads. Use of the non-speculative and truly decoupled threads produced by DSWP can increase execution efficiency and provide significant latency tolerance, ...

• Type: Conference
• Year: 2005
• Where: MICRO
• Authors: Guilherme Ottoni, Ram Rangan, Adam Stoler, David I. August
• Keywords: Automatic Compiler Implementation, Chip Multiprocessor, Compiler Implementation, Hardware, MICRO 2005