661 search results - page 7 / 133 » Increasing Processor Performance by Implementing Deeper Pipe... |
CODES
2001
IEEE
13 years 11 months ago
2001
IEEE
The paper proposes a novel software-pipelining algorithm, Register Sensitive Force Directed Retiming Algorithm (RSFDRA), suitable for optimizing compilers targeting embedded VLIW ...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
In many workloads, 25% to 50% of instructions have slack allowing them to be delayed without impacting performance. To exploit this slack, processors may implement more power-efï¬...
ISCA
2002
IEEE
14 years 8 days ago
2002
IEEE
The impact of pipeline length on the performance of a microprocessor is explored both theoretically and by simulation. An analytical theory is presented that shows two opposing ar...
ICPP
1991
IEEE
13 years 11 months ago
1991
IEEE
The memory consistency model supported by a multiprocessor directly affects its performance. Thus, several attempts have been made to relax the consistency models to allow for mor...
NOCS
2007
IEEE
14 years 1 months ago
2007
IEEE
— Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets...