Sciweavers

1139 search results - page 191 / 228
» Increasing the throughput of HomePNA
Sort
View
SIGCOMM
2009
ACM
14 years 5 months ago
SmartRE: an architecture for coordinated network-wide redundancy elimination
Application-independent Redundancy Elimination (RE), or identifying and removing repeated content from network transfers, has been used with great success for improving network pe...
Ashok Anand, Vyas Sekar, Aditya Akella
ACISICIS
2005
IEEE
14 years 4 months ago
An Effective Cache Overlapping Storage Structure for SMT Processors
Simultaneous Multithreaded (SMT) processors improve the instruction throughput by allowing fetching and running instructions from several threads simultaneously at a single cycle....
Liqiang He, Zhiyong Liu
ASPLOS
2000
ACM
14 years 3 months ago
Thread Level Parallelism and Interactive Performance of Desktop Applications
Multiprocessing is already prevalent in servers where multiple clients present an obvious source of thread-level parallelism. However, the case for multiprocessing is less clear f...
Krisztián Flautner, Richard Uhlig, Steven K...
WSC
1997
13 years 12 months ago
AutoSched Tutorial
The AutoSchedTM finite capacity planning and scheduling tool helps you increase throughput, reduce in-process inventory, and increase equipment and personnel utilization. AutoSche...
Bill Lindler
GLOBECOM
2007
IEEE
13 years 10 months ago
Multi-Class QoS in 802.11 Networks Using Gentle Decrease of Multiple Contention Windows
—IEEE 802.11 Distributed Coordination Function (DCF) uses a binary exponential backoff algorithm to arbitrate simultaneous channel access by multiple stations. When a station sen...
Bushra Anjum, Zartash Afzal Uzmi