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INFOCOM
2006
IEEE
14 years 4 months ago
Accelerating Simulation of Large-Scale IP Networks: A Network Invariant Preserving Approach
— In this paper, we propose a simulation framework, TranSim, that reduces the rate at which packet-events are generated, in order to accelerate large-scale simulation of IP netwo...
Hwangnam Kim, Hyuk Lim, Jennifer C. Hou
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 4 months ago
Virtually Pipelined Network Memory
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
Banit Agrawal, Timothy Sherwood
MICRO
2006
IEEE
98views Hardware» more  MICRO 2006»
14 years 4 months ago
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
The advent of deep sub-micron technology has recently highlighted the criticality of the on-chip interconnects. As diminishing feature sizes have led to increases in global wiring...
Chrysostomos Nicopoulos, Dongkook Park, Jongman Ki...
INTERSENSE
2006
ACM
14 years 4 months ago
QoS-aware mesh construction to enhance multicast routing in mobile ad hoc networks
— Mobile Ad-hoc Networks (MANETs) are seen as an essential technology to support future Pervasive Computing Scenarios and 4G networks. In a MANET, efficient support of multipoint...
Harald Tebbe, Andreas J. Kassler, Pedro M. Ruiz
IPPS
2005
IEEE
14 years 4 months ago
Runtime Empirical Selection of Loop Schedulers on Hyperthreaded SMPs
Hyperthreaded (HT) and simultaneous multithreaded (SMT) processors are now available in commodity workstations and servers. This technology is designed to increase throughput by e...
Yun Zhang, Michael Voss