Sciweavers

1139 search results - page 218 / 228
» Increasing the throughput of HomePNA
Sort
View
FPGA
1999
ACM
174views FPGA» more  FPGA 1999»
14 years 2 months ago
Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs
Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimized towards specific applications...
Peter Kollig, Bashir M. Al-Hashimi
ICDE
1998
IEEE
124views Database» more  ICDE 1998»
14 years 2 months ago
Compressing Relations and Indexes
We propose a new compression algorithm that is tailored to database applications. It can be applied to a collection of records, and is especially e ective for records with many lo...
Jonathan Goldstein, Raghu Ramakrishnan, Uri Shaft
ICCCN
1997
IEEE
14 years 2 months ago
Design and implementation of a QoS capable switch-router
Rapid expansion has strained the capabilities of the Internet infrastructure. Emerging audio and video applications place further demands on already overloaded network elements, e...
Erol Basturk, Alexander Birman, G. Delp, Roch Gu&e...
ISCA
1997
IEEE
108views Hardware» more  ISCA 1997»
14 years 2 months ago
The SGI Origin: A ccNUMA Highly Scalable Server
The SGI Origin 2000 is a cache-coherent non-uniform memory access (ccNUMA) multiprocessor designed and manufactured by Silicon Graphics, Inc. The Origin system was designed from t...
James Laudon, Daniel Lenoski
FC
1997
Springer
86views Cryptology» more  FC 1997»
14 years 2 months ago
The SPEED Cipher
Abstract. SPEED is a private key block cipher. It supports three variable parameters: (1) data length — the length of a plaintext/ciphertext of SPEED can be 64, 128 or 256 bits. ...
Yuliang Zheng