1139 search results - page 80 / 228 » Increasing the throughput of HomePNA |
FCCM
2002
IEEE
14 years 1 months ago
2002
IEEE
C-slow retiming (changing a design to support multiple instances of a computation) and datapath-aware placement have long been advocated by members of the FPGA synthesis community...
EUROPAR
2004
Springer
14 years 20 days ago
2004
Springer
The trend of data intensive grid applications has brought grid storage protocols and servers into focus. The objective of this study is to gain an understanding of how time is spen...
COMCOM
2010
13 years 9 months ago
2010
We study the interaction between the MIMD (Multiplicative Increase Multiplicative Decrease) congestion control and a bottleneck router with Drop Tail buffer. We consider the probl...
INFORMATICALT
2006
13 years 9 months ago
2006
In this paper optimization of DSR is achieved using New Link Cache structure and Source Transparent Route Maintenance Method. The new link cache effectively utilizes the memory by ...
JEC
2006
13 years 9 months ago
2006
Chip multi-processors (CMP) are rapidly emerging as an important design paradigm for both high performance and embedded processors. These machines provide an important performance...