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» Incremental formal design verification
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FORTE
2010
14 years 10 days ago
On Efficient Models for Model Checking Message-Passing Distributed Protocols
Abstract. The complexity of distributed algorithms, such as state machine replication, motivates the use of formal methods to assist correctness verification. The design of the for...
Péter Bokor, Marco Serafini, Neeraj Suri
CSE
2009
IEEE
13 years 8 months ago
Verifying the Interplay of Authorization Policies and Workflow in Service-Oriented Architectures
Abstract--A widespread design approach in distributed applications based on the service-oriented paradigm, such as web-services, consists of clearly separating the enforcement of a...
Michele Barletta, Silvio Ranise, Luca Viganò...
KCAP
2009
ACM
14 years 5 months ago
A catalogue of OWL ontology antipatterns
Debugging inconsistent OWL ontologies is a timeconsuming task. Debugging services included in existing ontology engineering tools are still far from providing adequate support to ...
Catherine Roussey, Óscar Corcho, Luis Manue...
DATE
2005
IEEE
164views Hardware» more  DATE 2005»
14 years 4 months ago
Automated Synthesis of Assertion Monitors using Visual Specifications
Automated synthesis of monitors from high-level properties plays a significant role in assertion-based verification. We present here a methodology to synthesize assertion monitors...
Ambar A. Gadkari, S. Ramesh
FMCAD
2000
Springer
14 years 2 months ago
B2M: A Semantic Based Tool for BLIF Hardware Descriptions
BLIF is a hardware description language designed for the hierarchical description of sequential circuits. We give a denotational semantics for BLIF-MV, a popular dialect of BLIF, t...
David A. Basin, Stefan Friedrich, Sebastian Mö...