193 search results - page 13 / 39 » Incremental logic rectification |
ASPDAC
2005
ACM
14 years 1 months ago
2005
ACM
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...
CAV
2005
Springer
14 years 1 months ago
2005
Springer
Bounded model checking is an efficient method for finding bugs in system designs. The major drawback of the basic method is that it cannot prove properties, only disprove them. R...
DATE
2000
IEEE
14 years 1 days ago
2000
IEEE
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...
TSE
2010
13 years 2 months ago
2010
Recent advances in mechanical techniques for systematic testing have increased our ability to automatically find subtle bugs, and hence to deploy more dependable software. This pap...
RSP
2003
IEEE
14 years 27 days ago
2003
IEEE
The paper shows the outlines of the SLAM system and how its design is suitable for automating rapid prototyping. The system includes a very expressive object oriented specificati...