36 search results - page 6 / 8 » Informed Multi-Process Prefetching and Caching |
PLDI
1999
ACM
13 years 12 months ago
1999
ACM
Hardware trends have produced an increasing disparity between processor speeds and memory access times. While a variety of techniques for tolerating or reducing memory latency hav...
ASPLOS
2009
ACM
14 years 8 months ago
2009
ACM
Modern processors use branch target buffers (BTBs) to predict the target address of branches such that they can fetch ahead in the instruction stream increasing concurrency and pe...
MDM
2005
Springer
14 years 1 months ago
2005
Springer
Data access prediction has been proposed as a mechanism to overcome latency lag, and more recently as a means of conserving energy in mobile systems. We present a fully adaptive p...
IEEEPACT
2006
IEEE
14 years 1 months ago
2006
IEEE
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
IEEEPACT
2002
IEEE
14 years 17 days ago
2002
IEEE
Simultaneous Multithreading (SMT) processors achieve high processor throughput at the expense of single-thread performance. This paper investigates resource allocation policies fo...