386 search results - page 4 / 78 » Informing Memory Operations: Providing Memory Performance Fe... |
PATMOS
2005
Springer
14 years 29 days ago
2005
Springer
Abstract. The load-store queue (LQ-SQ) of modern superscalar processors is responsible for keeping the order of memory operations. As the performance gap between processing speed a...
EUROPAR
1999
Springer
13 years 11 months ago
1999
Springer
Processor cycle time continues to decrease faster than main memory access times, placing higher demands on cache memory hierarchy performance. To meet these demands, conventional ...
COMCOM
2006
13 years 7 months ago
2006
The needs for run-time data storage in modern wired and wireless network applications are increasing. Additionally, the nature of these applications is very dynamic, resulting in ...
PDP
2005
IEEE
14 years 1 months ago
2005
IEEE
Clusters of SMPs are becoming increasingly common. However, the shared memory design of SMPs and the consequential contention between system processors for access to main memory c...
ISCA
1997
IEEE
13 years 11 months ago
1997
IEEE
Prefetching is one approach to reducing the latency of memory operations in modern computer systems. In this paper, we describe the Markov prefetcher. This prefetcher acts as an i...