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ISPASS
2010
IEEE
14 years 2 months ago
Synthesizing memory-level parallelism aware miniature clones for SPEC CPU2006 and ImplantBench workloads
Abstract—We generate and provide miniature synthetic benchmark clones for modern workloads to solve two pre-silicon design challenges, namely: 1) huge simulation time (weeks to m...
Karthik Ganesan, Jungho Jo, Lizy K. John
ACMSE
2004
ACM
14 years 1 months ago
Execution characteristics of SPEC CPU2000 benchmarks: Intel C++ vs. Microsoft VC++
Modern processors include features such as deep pipelining, multilevel cache hierarchy, branch predictors, out of order execution engine, and advanced floating point and multimedi...
Swathi Tanjore Gurumani, Aleksandar Milenkovic
VEE
2009
ACM
130views Virtualization» more  VEE 2009»
14 years 6 days ago
Post-copy based live virtual machine migration using adaptive pre-paging and dynamic self-ballooning
We present the design, implementation, and evaluation of post-copy based live migration for virtual machines (VMs) across a Gigabit LAN. Live migration is an indispensable feature...
Michael R. Hines, Kartik Gopalan
IISWC
2006
IEEE
14 years 1 months ago
Performance Characterization of SPEC CPU2006 Integer Benchmarks on x86-64 Architecture
— As x86-64 processors become the CPU of choice for the personal computer market, it becomes increasingly important to understand the performance we can expect by migrating appli...
Dong Ye, Joydeep Ray, Christophe Harle, David R. K...
ICCD
2001
IEEE
98views Hardware» more  ICCD 2001»
14 years 4 months ago
In-Line Interrupt Handling for Software-Managed TLBs
The general-purpose precise interrupt mechanism, which has long been used to handle exceptional conditions that occur infrequently, is now being used increasingly often to handle ...
Aamer Jaleel, Bruce L. Jacob